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| PD - _____ PRELIMINARY IRFZ34N HEXFET (R) Power MOSFET Advanced Process Technology Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Fully Avalanche Rated VDSS = 55V RDS(on) = 0.040 ID = 26A Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry. Absolute Maximum Ratings Parameter ID @ T C = 25C ID @ T C = 100C IDM PD @T C = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, V GS @ 10V Continuous Drain Current, V GS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw. Max. 26 18 100 56 0.37 20 110 16 5.6 4.6 -55 to + 175 300 (1.6mm from case) 10 lbf*in (1.1N*m) Units A W W/C V mJ A mJ V/ns C Thermal Resistance Parameter RJC RCS RJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient Min. ---- ---- ---- Typ. ---- 0.50 ---- Max. 2.7 ---- 62 Units C/W 8/29/95 IRFZ34N Electrical Characteristics @ TJ = 25C (unless otherwise specified) V(BR)DSS V(BR)DSS/TJ RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. 55 --- --- 2.0 6.5 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- 0.052 --- --- --- --- --- --- --- --- --- --- 7.0 49 31 40 4.5 7.5 700 240 100 Max. Units Conditions --- V VGS = 0V, I D = 250A --- V/C Reference to 25C, I D = 1mA 0.040 VGS = 10V, I D = 16A 4.0 V VDS = VGS, ID = 250A --- S VDS = 25V, ID = 16A 25 VDS = 55V, VGS = 0V A 250 VDS = 44V, VGS = 0V, T J = 150C 100 VGS = 20V nA -100 VGS = -20V 34 ID = 16A 6.8 nC VDS = 44V 14 VGS = 10V, See Fig. 6 and 13 --- VDD = 28V --- ID = 16A ns --- RG = 18 --- RD = 1.8, See Fig. 10 Between lead, --- 6mm (0.25in.) nH from package --- and center of die contact --- VGS = 0V --- pF VDS = 25V --- = 1.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units --- --- --- --- --- --- --- --- 57 130 26 A 100 1.6 86 200 V ns nC Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, I S = 16A, V GS = 0V TJ = 25C, I F = 16A di/dt = 100A/s S+LD) Intrinsic turn-on time is negligible (turn-on is dominated by L Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) ISD 16 A, di/dt 420A/s, V DD V(BR)DSS, T J 175C Pulse width 300s; duty cycle 2%. VDD = 25V, starting T J = 25C, L = 610H R G = 25, IAS = 16A. (See Figure 12) IRFZ34N 1000 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 1000 I , Drain-to-Source Current (A) D 100 I , Drain-to-Source Current (A) D VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 100 10 10 4.5V 4.5V 20s PULSE WIDTH TC = 25C 1 10 100 1 0.1 A 1 0.1 20s PULSE WIDTH TC = 175C 1 10 100 A VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics, TC = 25oC Fig 2. Typical Output Characteristics, TC = 175oC 100 2.4 R DS(on) , Drain-to-Source On Resistance (Normalized) I D = 26A I D , Drain-to-Source Current (A) TJ = 25C TJ = 175C 2.0 1.6 10 1.2 0.8 0.4 1 4 5 6 7 VDS = 25V 20s PULSE WIDTH 8 9 10 A 0.0 -60 -40 -20 0 20 40 60 VGS = 10V 80 100 120 140 160 180 A VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature (C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature IRFZ34N 1200 1000 VGS , Gate-to-Source Voltage (V) V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd Ciss C oss = Cds + C gd 20 I D = 16A V DS = 44V V DS = 28V 16 C, Capacitance (pF) 800 Coss 600 12 8 400 Crss 200 4 0 1 10 100 A 0 0 10 20 FOR TEST CIRCUIT SEE FIGURE 13 30 40 A VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 1000 ISD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY RDS(on) 100 ID , Drain Current (A) 100 10s TJ = 175C TJ = 25C 100s 10 1ms 10 1 0.4 0.8 1.2 1.6 VGS = 0V A 1 1 TC = 25C TJ = 175C Single Pulse 10 10ms A 100 2.0 VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area IRFZ34N VDS 30 RD VGS RG D.U.T. VDD 25 ID, Drain Current (Amps) 10 V 20 Pulse Width 1 s Duty Factor 0.1 % 15 Fig 10a. Switching Time Test Circuit 10 5 0 25 50 75 100 125 150 A 175 TC , Case Temperature (C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig 10b. Switching Time Waveforms 10 Thermal Response (Z thJC ) D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) N otes : 1 . D uty fac tor D = t 1 /t 2 PD M t 1 t2 0.01 0.00001 2. P ea k T J = P D M x Z thJ C + T C A 1 0.0001 0.001 0.01 0.1 t 1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case IRFZ34N EAS , Single Pulse Avalanche Energy (mJ) 250 TOP 200 BOTTOM ID 6.5A 11A 16A 10 V 150 Fig 12a. Unclamped Inductive Test Circuit 100 50 0 VDD = 25V 25 50 75 100 125 150 A 175 Starting TJ , Junction Temperature (C) Fig 12b. Unclamped Inductive Waveforms Fig 12c. Maximum Avalanche Energy Vs. Drain Current 10 V Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit Appendix A: Figure 14, Peak Diode Recovery dv/dt Test Circuit Appendix B: Package Outline Mechanical Drawing Appendix C: Part Marking Information IRFZ34N Appendix A Peak Diode Recovery dv/dt Test Circuit D.U.T Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer RG * * * * dv/dt controlled by R G Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD * * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS IRFZ34N Package Outline TO-220AB Outline Dimensions are shown in millimeters (inches) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240) -B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048) Appendix B 2.87 (.113) 2.62 (.103) 4 15.24 (.600) 14.84 (.584) 1.15 (.045) MIN 1 2 3 LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 14.09 (.555) 13.47 (.530) 4.06 (.160) 3.55 (.140) 3X 1.40 (.055) 3X 1.15 (.045) 2.54 (.100) 0.93 (.037) 0.69 (.027) M BAM 3X 0.55 (.022) 0.46 (.018) 0.36 (.014) 2.92 (.115) 2.64 (.104) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. Part Marking Information TO-220AB Appendix C EXAMPLE : THIS IS AN IRF1010 WITH ASSEMBLY LOT CODE 9B1M A INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER IRF1010 9246 9B 1M DATE CODE (YYWW) YY = YEAR WW = WEEK |
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